By Jon Stokes | Published: April 08, 2008 - 11:47PM CT
SSE 4.2, virtualization, and multithreading
Intel has added a number of new instructions to Nehalem and it has sped up others. The 4.2 version of Intel's SSE vector extensions takes the x86 ISA back to the future just a bit by adding new string manipulation instructions. I say "back to the future" because ISA-level support for string processing is a hallmark of CISC architectures that was actively deprecated in the post-RISC years; typically, when a writer wants to give an example of crufty old corners of the x86 ISA that have caused pain for chip architects, string manipulation instructions are what he or she reaches for. But the new SSE 4.2 string instructions are aimed at accelerating XML processing, which makes them Web-friendly and therefore modern (i.e., not crufty).
SSE 4.2 also includes a CRC instruction that accelerate storage and networking applications, as well as a POPCNT instruction that's useful for a variety of pattern matching tasks. Also, to provide better support for multithreaded applications, Intel decreased the latency of its thread synchronization primitives.
On the virtualization front, Nehalem speeds up VM transitions and has some substantial improvements, which I won't detail here, to its virtual memory system that will greatly reduce the number of such transitions required by the hypervisor.
Conclusions: it's about the platform
With the advent of Nehalem, Intel makes the giant leap from what is fundamentally still its decades-old monolithic-processor-plus-FSB platform to a fully modern SoC and NUMA (see diagram below) platform.
Intel's current four-socket Xeon platform vs. Nehalem's fully connected NUMA topology. Note that main memory is never more than one hop away from a socket.
This leap is long overdue (AMD was there years ago), but when Intel makes it in the fourth quarter of this year, it will change everything about its broader platform picture. The increase in bandwidth alone will improve performance on multisocket servers, and even desktop and mobile platforms will benefit from the higher levels of integration and performance that the integrated memory controller brings with it.
In sum, Intel's entire processor product line will benefit from the large structural changes that I've outlined here, as well as from the smaller, core-specific improvements that Nehalem embodies. And from here on out, Nehalem's mix-and-match approach to products and platforms will be par for the course for Intel, as well as for rival AMD.
With the launch of the first four-core, eight-thread Nehalem, the future of hardware will have arrived; and with all of that parallelism available, the performance ball will be squarely in the software industry's court. But that's a topic for another day.
